Features:
The whole decoder board uses CPLD as data processing. Because CPLD is parallel processing, it will not be serial processing like the peripheral logic chip, of which delay between all the gates will accumulate. The delay to the last data is very large. The resulting signal jitter cannot be ignored. Therefore, the R2R DAC developed by CPLD has advantages.
This decoder board has mid-tone accuracy, deep bass diving, and high-tone accuracy. The overall experience shows that the degree of separation is better than that of an integrated IC solution
Name: R2R LADDER SOURCE DA Convert
Version: 5.0 (after 5 times of proofing and debugging, so it comes out as 5.0 version)
Size: Length 146.8mm Width 66.9mm
Voltage: DC Voltage +5v Logic Circuit Power Supply
DC voltage +15V 0V -15V Power supply for analog amplifier circuits
Signal input: 4-wire I2S (Philips IIS format) does not support left alignment right alignment GND BCK LRCK DATA
Support sample rate up to the highest tested PCM384KHZ normal work, does not support DSD format.
Tested PCM384KHZ works normally (the highest sampling rate), does not support DSD format.
Outputs: single-ended version: stereo output. That is, one board two channels output( left and right sound channels)
